Lithography process and system with enhanced overlay quality
US10146141B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/705
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.