System and method for performing partial cache line writes without fill-reads or byte enables
US10146691B2 · kind B2 · utility
3Cited by
3References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.