Saurabh Sharma
45Patents
4h-index
90Co-inventors
62Inventor score
Filing activity: Mar 24, 2009 → Jan 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10122723B1 | Supervised contact list for user accounts | Electricity | 14 | Active |
| US10424107B2 | Hierarchical depth buffer back annotaton | Physics | 5 | Active |
| US9824412B2 | Position-only shading pipeline | Physics | 4 | Active |
| US10068249B1 | Inventory forecasting for bidded ad exchange | Physics | 4 | Active |
| US10102609B1 | Low granularity coarse depth test efficiency enhancement | Emerging Cross-Sectional Technologies | 4 | Active |
| US10146691B2 | System and method for performing partial cache line writes without fill-reads or byte enables | Physics | 3 | Active |
| US10861126B1 | Asynchronous execution mechanism | Emerging Cross-Sectional Technologies | 3 | Active |
| US11308648B2 | Compressing texture data on a per-channel basis | Electricity | 2 | Active |
| US8458431B2 | Expanding memory size | Physics | 1 | Active |
| US10369989B2 | Parking assistance system and method for controlling the same | Physics | 1 | Active |
| US9268691B2 | Fast mechanism for accessing 2n±1 interleaved memory system | Physics | 1 | Active |
| US11694367B2 | Compressing texture data on a per-channel basis | Electricity | 0 | Active |
| US9846962B2 | Optimizing clipping operations in position only shading tile deferred renderers | Physics | 0 | Active |
| US11403805B2 | Position-based rendering apparatus and method for multi-die/GPU graphics processing | Physics | 0 | Active |
| US12189534B2 | Cache blocking for dispatches | Physics | 0 | Active |
| US11250539B2 | Low granularity coarse depth test efficiency enhancement | Emerging Cross-Sectional Technologies | 0 | Active |
| US10262388B2 | Frequent data value compression for graphics processing units | Physics | 0 | Active |
| US11494867B2 | Asynchronous execution mechanism | Emerging Cross-Sectional Technologies | 0 | Active |
| US12293462B2 | Tile sequencing mechanism | Physics | 0 | Active |
| US11204801B2 | Method and apparatus for scheduling thread order to improve cache efficiency | Emerging Cross-Sectional Technologies | 0 | Active |
| US10748242B2 | Low granularity coarse depth test efficiency enhancement | Emerging Cross-Sectional Technologies | 0 | Active |
| US9836809B2 | Method and apparatus for adaptive pixel hashing for graphics processors | Physics | 0 | Active |
| US12117939B2 | Stochastic optimization of surface cacheability in parallel processing units | Physics | 0 | Active |
| US11710269B2 | Position-based rendering apparatus and method for multi-die/GPU graphics processing | Physics | 0 | Active |
| US10546362B2 | Method and apparatus for adaptive pixel hashing for graphics processors | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.