Barrier for preventing eutectic break-through in through-substrate vias
US10147642B1 · kind B1 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Apr 25, 2013 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.