Method and structure for process limiting yield testing

US10147659B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Uwe Dersch · Radebeul, DE
• Ricardo P. Mikalo · Stadtroda, DE
• Thomas Merbeth · Dresden, DE

Key dates

• Filing date: Jul 18, 2017
• Grant date: Dec 4, 2018
• Expiry date: Jul 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.