Semiconductor memory device and method for manufacturing same
US10147736B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Nov 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76847
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a semiconductor film extending in stacking direction of the stacked body; an interconnect layer extending in the stacking direction of the stacked body and a first direction crossing the stacking direction; and an insulating film. The interconnect layer includes: a core film extending in the stacking direction and the first direction; an intermediate film provided integrally between the core film and the plurality of electrode layers and between the core film and the substrate; and a first conductive film provided integrally between the intermediate film and the plurality of electrode layers and between the intermediate film and the substrate, being in contact with the substrate, and having an upper surface flush with an upper surface of the intermediate film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.