Process for fabricating a field effect transistor having a coating gate
US10147788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Oct 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.