Patent · US Active

FinFET devices including recessed source/drain regions having optimized depths

US10147793B2 · kind B2 · utility

1Cited by
13References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 27, 2014
Grant dateDec 4, 2018
Priority date
Expiry dateJun 28, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/62

Abstract

A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.