FinFET devices including recessed source/drain regions having optimized depths
US10147793B2 · kind B2 · utility
1Cited by
13References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 2014 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.