Bit-flipping LDPC decoding algorithm with hard channel information
US10148287B2 · kind B2 · utility
3Cited by
4References
15Claims
0Family size
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Key dates
| Filing date | Nov 8, 2016 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.