Aman Bhatia
115Patents
6h-index
32Co-inventors
66Inventor score
Filing activity: Nov 20, 2015 → Mar 16, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9998148B2 | Techniques for low complexity turbo product code decoding | Electricity | 21 | Active |
| US11108407B1 | Performance of a bit flipping (BF) decoder of an error correction system | Electricity | 12 | Active |
| US10707899B2 | Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes | Electricity | 9 | Active |
| US10491243B2 | Deep learning for low-density parity-check (LDPC) decoding | Electricity | 9 | Active |
| US11381253B1 | Decoding codeword based on higher order information | Electricity | 9 | Active |
| US10700706B2 | Memory system with decoders and method of operating such memory system and decoders | Physics | 7 | Active |
| US11146289B2 | Techniques to use intrinsic information for a bit-flipping error correction control decoder | Physics | 5 | Active |
| US10884947B2 | Methods and memory systems for address mapping | Emerging Cross-Sectional Technologies | 5 | Active |
| US10218388B2 | Techniques for low complexity soft decoder for turbo product codes | Electricity | 4 | Active |
| US10419024B2 | Early termination of low-density parity-check (LDPC) decoding | Electricity | 4 | Active |
| US10388400B2 | Generalized product codes for flash storage | Physics | 4 | Active |
| US10484008B2 | Memory system with on-the-fly error detection and termination and operating method thereof | Electricity | 4 | Active |
| US10389383B2 | Low-complexity LDPC encoder | Electricity | 4 | Active |
| US10303364B2 | Techniques for low-latency chase decoding of turbo product codes with soft information | Electricity | 4 | Active |
| US11515897B2 | Data storage device | Electricity | 4 | Active |
| US11316532B1 | Decoding of low-density parity-check codes with high-degree variable nodes | Electricity | 4 | Active |
| US10148287B2 | Bit-flipping LDPC decoding algorithm with hard channel information | Electricity | 3 | Active |
| US11393539B2 | Systems and methods for determining change of read threshold voltage | Physics | 3 | Active |
| US11367488B2 | Memory system and method for read operation based on grouping of word lines | Physics | 3 | Active |
| US10432363B2 | Page health prediction using product codes decoder in NAND flash storage | Physics | 3 | Active |
| US11190212B1 | Dynamic control of quasi-cyclic low-density parity-check bit-flipping decoder | Electricity | 3 | Active |
| US10672497B2 | Memory system and method for bad block management | Physics | 3 | Active |
| US10949113B2 | Retention aware block mapping in flash-based solid state drives | Physics | 3 | Active |
| US10601546B2 | Dynamic interleaver change for bit line failures in NAND flash storage | Physics | 2 | Active |
| US10997017B2 | Neighbor assisted correction error recovery for memory system and method thereof | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.