Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit

US10151797B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Tripti Gupta · Noida, IN

Key dates

• Filing date: Jul 29, 2016
• Grant date: Dec 11, 2018
• Expiry date: Oct 31, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318572
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.