Hierarchically aware interior pinning for large synthesis blocks
US10157255B2 · kind B2 · utility
2Cited by
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18Claims
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Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.