Self-aligned interconnection for integrated circuits
US10157788B2 · kind B2 · utility
3Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2016 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Oct 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.