Multi-gate device and method of fabrication thereof
US10157799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2018 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.