Patent · US Active

Integrated circuit (IC) package and package substrate comprising stacked vias

US10157824B2 · kind B2 · utility

1Cited by

5References

31Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Kuiwon Kang · San Diego, US
Houssam Jomaa · San Diego, US
Layal Rouhana · San Diego, US
Seongryul Choi · Seongnam-si, KR

Key dates

Filing date	Aug 16, 2017
Grant date	Dec 18, 2018
Priority date	—
Expiry date	Aug 16, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.