Semiconductor device with memory structure
US10157963B1 · kind B1 · utility
3Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A semiconductor device includes a substrate and a memory structure disposed above the substrate. An embodied memory structure includes a bottom electrode disposed above the substrate, a barrier layer disposed at the bottom electrode, a resistance switching layer disposed on the bottom electrode and above the barrier layer, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. A bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.