Patent · US Active

Methods for forming integrated circuits that include a dummy gate structure

US10157996B2 · kind B2 · utility

1Cited by

1References

20Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Elliot John Smith · Dresden, DE
Jan Hoentschel · Dresden, DE
Nigel Chan · Sunnyvale, US
Sven Beyer · Dresden, DE

Key dates

Filing date	Jul 13, 2017
Grant date	Dec 18, 2018
Priority date	—
Expiry date	Jul 13, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.