Elliot John Smith
34Patents
4h-index
24Co-inventors
55Inventor score
Filing activity: Jan 12, 2015 → Aug 19, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10483154B1 | Front-end-of-line device structure and method of forming such a front-end-of-line device structure | Electricity | 375 | Active |
| US9793372B1 | Integrated circuit including a dummy gate structure and method for the formation thereof | Electricity | 12 | Active |
| US9608112B2 | BULEX contacts in advanced FDSOI techniques | Electricity | 10 | Active |
| US9590118B1 | Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure | Electricity | 8 | Active |
| US9847347B1 | Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof | Electricity | 4 | Active |
| US9514942B1 | Method of forming a gate mask for fabricating a structure of gate lines | Electricity | 4 | Active |
| US9698179B2 | Capacitor structure and method of forming a capacitor structure | Electricity | 3 | Active |
| US9685336B1 | Process monitoring for gate cut mask | Electricity | 2 | Active |
| US10319827B2 | High voltage transistor using buried insulating layer as gate dielectric | Electricity | 2 | Active |
| US10199259B1 | Technique for defining active regions of semiconductor devices with reduced lithography effort | Electricity | 2 | Active |
| US9666052B1 | Portable environment monitoring and early warning system for babies | Human Necessities | 2 | Active |
| US10559490B1 | Dual-depth STI cavity extension and method of production thereof | Electricity | 1 | Active |
| US10707330B2 | Semiconductor device with interconnect to source/drain | Electricity | 1 | Active |
| US10177163B1 | SOI-based floating gate memory cell | Electricity | 1 | Active |
| US9953876B1 | Method of forming a semiconductor device structure and semiconductor device structure | Electricity | 1 | Active |
| US10593674B1 | Deep fence isolation for logic cells | Electricity | 1 | Active |
| US11031406B2 | Semiconductor devices having silicon/germanium active regions with different germanium concentrations | Electricity | 1 | Active |
| US10396084B1 | Semiconductor devices including self-aligned active regions for planar transistor architecture | Electricity | 1 | Active |
| US10157996B2 | Methods for forming integrated circuits that include a dummy gate structure | Electricity | 1 | Active |
| US12013493B2 | Lidar system including light emitter for multiple receiving units | Physics | 0 | Active |
| US11745453B2 | Method of making and using a reusable mold for fabrication of optical elements | Performing Operations; Transporting | 0 | Active |
| US9923076B2 | Gate patterning for AC and DC performance boost | Electricity | 0 | Active |
| US10340359B2 | Gate structure with dual width electrode layer | Electricity | 0 | Active |
| US10103224B2 | Semiconductor structure including a trench capping layer | Electricity | 0 | Active |
| US10418380B2 | High-voltage transistor device with thick gate insulation layers | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.