Memory operation threshold adjustment based on bit line integrity data
US10162538B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 30, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.