Double data rate (DDR) memory read latency reduction
US10162773B1 · kind B1 · utility
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4References
20Claims
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Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Nov 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.