Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method
US10163635B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.