Method of manufacturing semiconductor device by applying molding layer in substrate groove
US10163710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.