Method of forming self-alignment contact
US10163719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.