Gate stacks
US10164044B2 · kind B2 · utility
1Cited by
9References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.