Eric Blomiley
27Patents
5h-index
21Co-inventors
65Inventor score
Filing activity: Apr 18, 2003 → Sep 9, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7557002B2 | Methods of forming transistor devices | Electricity | 27 | Active |
| US7531395B2 | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors | Electricity | 21 | Expired |
| US7956416B2 | Integrated circuitry | Electricity | 18 | Active |
| US7528424B2 | Integrated circuitry | Electricity | 9 | Active |
| US7276416B2 | Method of forming a vertical transistor | Electricity | 6 | Expired |
| US8035129B2 | Integrated circuitry | Electricity | 5 | Active |
| US7132355B2 | Method of forming a layer comprising epitaxial silicon and a field effect transistor | Electricity | 5 | Expired |
| US8216935B2 | Methods of forming transistor gate constructions, methods of forming NAND transistor gate constructions, and methods forming DRAM transistor gate constructions | Electricity | 5 | Active |
| US8426919B2 | Integrated circuitry | Electricity | 5 | Active |
| US9972628B1 | Conductive structures, wordlines and transistors | Electricity | 4 | Active |
| US7144779B2 | Method of forming epitaxial silicon-comprising material | Electricity | 4 | Expired |
| US6911367B2 | Methods of forming semiconductive materials having flattened surfaces; methods of forming isolation regions; and methods of forming elevated source/drain regions | Electricity | 3 | Expired |
| US7268023B2 | Method of forming a pseudo SOI substrate and semiconductor devices | Electricity | 3 | Expired |
| US7517758B2 | Method of forming a vertical transistor | Electricity | 2 | Expired |
| US7662649B2 | Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses | Chemistry; Metallurgy | 2 | Active |
| US8872252B2 | Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier | Electricity | 2 | Active |
| US7768036B2 | Integrated circuitry | Electricity | 1 | Active |
| US6987055B2 | Methods for deposition of semiconductor material | Electricity | 1 | Expired |
| US10164044B2 | Gate stacks | Electricity | 1 | Active |
| US10411017B2 | Multi-component conductive structures for semiconductor devices | Electricity | 1 | Active |
| US7585371B2 | Substrate susceptors for receiving semiconductor substrates to be deposited upon | Chemistry; Metallurgy | 1 | Expired |
| US7538392B2 | Pseudo SOI substrate and associated semiconductor devices | Electricity | 0 | Active |
| US7253085B2 | Deposition methods | Electricity | 0 | Expired |
| US10777651B2 | Gate stacks | Electricity | 0 | Active |
| US10991701B2 | Multi-component conductive structures for semiconductor devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.