Reducing metadata size in compressed memory systems of processor-based systems
US10169246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.