Memory system design using buffer(s) on a mother board
US10169258B2 · kind B2 · utility
3Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Sep 16, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.