Inventor · San Jose, CA, US

Henry Stracovsky

25Patents
14h-index
24Co-inventors
81Inventor score

Filing activity: Aug 10, 1998 → Aug 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6442644B1 Memory system having synchronous-link DRAM (SLDRAM) devices and controller Emerging Cross-Sectional Technologies 382 Expired
US6216178A Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution Physics 98 Expired
US9043674B2 Error detection and correction apparatus and method Electricity 68 Active
US6442666B1 Techniques for improving memory access in a virtual memory system Physics 42 Expired
US6195724A Methods and apparatus for prioritization of access to external devices Physics 33 Expired
US6510474B1 Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests Physics 30 Expired
US6378049B1 Universal memory controller Physics 24 Expired
US6587894B1 Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory Physics 23 Expired
US6374323B1 Computer memory conflict avoidance using page registers Physics 22 Expired
US6453370B1 Using of bank tag registers to avoid a background operation collision in memory systems Physics 20 Expired
US6430642B1 Methods and apparatus for prioritization of access to external devices Physics 18 Expired
US6286075A Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M Physics 18 Expired
US6385708B1 Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses Physics 18 Expired
US6532505B1 Universal resource access controller Physics 17 Expired
US6539440B1 Methods and apparatus for prediction of the time between two consecutive memory accesses Physics 10 Expired
US11294830B2 Training and operations with a double buffered memory topology Electricity 4 Active
US10613995B2 Training and operations with a double buffered memory topology Electricity 4 Active
US10169258B2 Memory system design using buffer(s) on a mother board Emerging Cross-Sectional Technologies 3 Active
US8495464B2 Reliability support in memory systems without error correcting code support Electricity 1 Active
US10614002B2 Memory system design using buffer(S) on a mother board Emerging Cross-Sectional Technologies 0 Active
US12141081B2 Training and operations with a double buffered memory topology Electricity 0 Active
US11537540B2 Memory system design using buffer(s) on a mother board Emerging Cross-Sectional Technologies 0 Active
US11003601B2 Memory system design using buffer(s) on a mother board Emerging Cross-Sectional Technologies 0 Active
US11907139B2 Memory system design using buffer(s) on a mother board Emerging Cross-Sectional Technologies 0 Active
US11768780B2 Training and operations with a double buffered memory topology Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.