3D memory device including shared select gate connections between memory blocks
US10170188B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.