Semiconductor device and method
US10170367B2 · kind B2 · utility
2Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Oct 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.