Selective blocking boundary placement for circuit locations requiring electromigration short-length
US10170416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Nov 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving copper (Cu), selectively recessing the Cu at one or more of the trenches corresponding to circuit locations requiring electromigration (EM) short-length, and forming self-aligned conducting caps over the one or more trenches where the Cu has been selectively recessed. The conducting caps can be tantalum nitride (TaN) caps. The method further includes forming a via extending into each of the trenches for receiving Cu. Additionally, the via for trenches including recessed Cu extends to the self-aligned conducting cap, whereas the via for trenches including non-recessed Cu extends to a top surface of the Cu.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.