Semiconductor memory device and method of forming the same
US10170481B2 · kind B2 · utility
1Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Mar 7, 2018 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Mar 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.