Integrated capacitors with nanosheet transistors
US10170548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2018 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.