Strained stacked nanosheet FETs and/or quantum well stacked nanosheet
US10170549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2015 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Apr 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/472
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.