Hardware double buffering using a special purpose computational unit
US10175912B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jul 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.