Inventor · San Jose, CA, US

Harshit Khaitan

32Patents
8h-index
15Co-inventors
64Inventor score

Filing activity: Oct 27, 2016 → Feb 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9710265B1 Neural network compute tile Physics 110 Active
US9836691B1 Neural network instruction set architecture Physics 76 Active
US10175980B2 Neural network compute tile Physics 34 Active
US10504022B2 Neural network accelerator with parameters resident on chip Physics 19 Active
US9959498B1 Neural network instruction set architecture Physics 19 Active
US10534607B2 Accessing data in multi-dimensional tensors using adders Physics 10 Active
US10496326B2 Hardware double buffering using a special purpose computational unit Physics 9 Active
US10802956B2 Accessing prologue and epilogue data Physics 8 Active
US11709783B1 Tensor data distribution using grid direct-memory access (DMA) controller Physics 8 Active
US9946539B1 Accessing data in multi-dimensional tensors using adders Physics 8 Active
US10248908B2 Alternative loop limits for accessing data in multi-dimensional tensors Physics 7 Active
US11467675B1 Multi-component detection of gestures Physics 4 Active
US10108538B1 Accessing prologue and epilogue data Physics 3 Active
US10175912B1 Hardware double buffering using a special purpose computational unit Physics 2 Active
US11704562B1 Architecture for virtual instructions Physics 2 Active
US11422801B2 Neural network compute tile Physics 1 Active
US11176493B2 Virtualizing external memory as local to a machine learning accelerator Emerging Cross-Sectional Technologies 1 Active
US12001893B1 Distributed synchronization scheme Physics 1 Active
US10885434B2 Alternative loop limits for accessing data in multi-dimensional tensors Physics 0 Active
US11893159B2 Multi-component detection of gestures Physics 0 Active
US11501144B2 Neural network accelerator with parameters resident on chip Physics 0 Active
US12061968B2 Neural network instruction set architecture Physics 0 Active
US11099772B2 Hardware double buffering using a special purpose computational unit Physics 0 Active
US11954580B2 Spatial tiling of compute arrays with shared control Physics 0 Active
US11922306B2 Tensor controller architecture Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.