Sorting numbers in hardware
US10175943B2 · kind B2 · utility
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6References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 26, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n−1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.