Power-up sequence protection circuit for avoiding unexpected power-up voltage
US10176883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jan 10, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.