Semiconductor package structure, package on package structure and packaging method
US10177099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.