Fan out semiconductor device including a plurality of semiconductor die
US10177119B2 · kind B2 · utility
5Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jun 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.