SOI-based floating gate memory cell
US10177163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2018 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative device disclosed a floating gate capacitor located in and above a first region of an SOI substrate located on a first side of an isolation trench and a transistor device located in and above a second region of the SOI substrate that is on the opposite side of the isolation trench. The device also includes a control gate formed in the bulk semiconductor layer in the first region and a gate structure that extends across the isolation trench and above the first and second regions. A first portion of the gate structure is positioned above the first region and the control gate and a second portion of the gate structure is positioned above the second region, wherein the first portion of the gate structure constitutes a floating gate for the floating gate capacitor and the second portion of the gate structure constitutes a transistor gate structure for the transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.