Storage device operations based on bit error rate (BER) estimate
US10180874B2 · kind B2 · utility
5Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Jun 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6325
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.