Method for fabricating a carrier-less silicon interposer
US10181411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Mar 6, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.