Three-dimensional non-volatile memory and manufacturing method thereof
US10181475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.