Multiple input signature register analysis for digital circuitry
US10184980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Dec 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.