Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

US10186011B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Eriko Nurvitadhi · Beaverton, US
• Balaji Vembu · Folsom, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Rajkishore Barik · Santa Clara, US
• Tsung-Han Lin · Campbell, US
• Kamal Sinha · Rancho Cordova, US
• Nadathur Rajagopalan Satish · Santa Clara, US
• Jeremy Bottleson · Rancho Cordova, US
• Farshad Akhbari · Chandler, US
• Altug Koker · Cameron Park, US
• Narayan Srinivasa · Thousand Oaks, US
• Dukhwan Kim · Mountain View, US
• Sara S. Baghsorkhi · San Jose, US
• Justin E. Gottschlich · Santa Clara, US
• Feng Chen · Shanghai, CN
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Kevin Nealis · San Jose, US
• Xiaoming Chen · Xi'an, CN
• Anbang Yao · Beijing, CN

Key dates

• Filing date: Apr 28, 2017
• Grant date: Jan 22, 2019
• Expiry date: Apr 28, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/098
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.