Hybrid stack write driver
US10186312B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Oct 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a memory array having memory cells and bitlines. A write driver is connected to the bitlines through column select transistors. A write assist circuit is connected to the write driver. The write assist circuit includes a common boost node, negative boost transistors, and a keeper transistor. The negative boost transistors are connected from the digit lines to the common boost node. The negative boost transistors selectively pull the bitlines of a selected cell of the memory array to ground during a write operation to the selected cell of the memory array. The write assist circuit may include a first negative boost transistor connected from a first digit line to the common boost node, a second negative boost transistor connected from a second digit line to the common boost node, and a keeper transistor connected from the common boost node to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.