Metal on both sides with clock gated-power and signal routing underneath
US10186484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2014 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.