Inventor · Hillsboro, OR, US

Kimin Jun

70Patents
5h-index
73Co-inventors
71Inventor score

Filing activity: Jun 30, 2011 → Jan 17, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9685436B2 Monolithic three-dimensional (3D) ICs with local inter-level interconnects Electricity 21 Active
US10872820B2 Integrated circuit structures Emerging Cross-Sectional Technologies 13 Active
US10068874B2 Method for direct integration of memory die to logic die without use of thru silicon vias (TSV) Electricity 11 Active
US10043797B2 Techniques for forming vertical transistor architectures Electricity 7 Active
US10797139B2 Methods of forming backside self-aligned vias and structures formed thereby Electricity 6 Active
US10297592B2 Monolithic three-dimensional (3D) ICs with local inter-level interconnects Electricity 5 Active
US10367070B2 Methods of forming backside self-aligned vias and structures formed thereby Electricity 5 Active
US11264493B2 Wrap-around source/drain method of making contacts for backside metals Electricity 5 Active
US11251156B2 Fabrication and use of through silicon vias on double sided interconnect device Electricity 4 Active
US11201221B2 Backside contact structures and fabrication for metal on both sides of devices Electricity 4 Active
US11594524B2 Fabrication and use of through silicon vias on double sided interconnect device Electricity 3 Active
US10700039B2 Silicon die with integrated high voltage devices Electricity 3 Active
US12107060B2 Microelectronic assemblies with inductors in direct bonding regions Electricity 3 Active
US10439057B2 Multi-gate high electron mobility transistors and methods of fabrication Electricity 3 Active
US10186484B2 Metal on both sides with clock gated-power and signal routing underneath Electricity 3 Active
US11658221B2 Backside contact structures and fabrication for metal on both sides of devices Electricity 2 Active
US11348897B2 Microelectronic assemblies Electricity 2 Active
US12062631B2 Microelectronic assemblies with inductors in direct bonding regions Electricity 2 Active
US10784358B2 Backside contact structures and fabrication for metal on both sides of devices Electricity 2 Active
US11251158B2 Monolithic chip stacking using a die with double-sided interconnect layers Electricity 2 Active
US11393818B2 Stacked transistors with Si PMOS and high mobility thin film transistor NMOS Electricity 1 Active
US11640961B2 III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts Electricity 1 Active
US11393777B2 Microelectronic assemblies Electricity 1 Active
US10763248B2 Multi-layer silicon/gallium nitride semiconductor Electricity 1 Active
US11676966B2 Stacked transistors having device strata with different channel widths Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.