Semiconductor package and method of fabricating the same
US10186500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2016 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.